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[VHDL-FPGA-Verilog] FFT的VHDL源代码

Description: FFT的VHDL源代码-fft vhdl source code
Platform: | Size: 29696 | Author: 阿林 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4bit ALU（运算逻辑单元）的设计给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Platform: | Size: 1024 | Author: chenyi | Hits:

[Other] f

Description: vhdl code for FIR filter
Platform: | Size: 1024 | Author: vovanich | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] 1.-VHDL-Code-For-BCD-To-Decimal-Decoder-By-Data-F

Description: 1. VHDL Code For BCD To Decimal Decoder By Data Flow Modelling
Platform: | Size: 45056 | Author: rik | Hits:

[Other] kehshechenxu

Description: 编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示；数据格式为1位起始位、8位数据位和一位停止位；上位计算机发送接收软件可使用“串口调试器“软件；发送和接收数据时，由两个LED分别指示。发挥：自动回发功能、接收到特殊字符（自定义）自动更改波特率。(A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button. Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively; The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit; The upper computer sends and receives the software, and the serial debugger can be used; When sending and receiving data, instructions are given by two LED respectively. Play: Auto postback function, receive special characters (custom), change baud rate automatically.)
Platform: | Size: 2948096 | Author: 淡淡的意识 | Hits:

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